High-performance and very large scale integration chips such as microprocessors, chipsets, system on-chips, application specific integrated circuits (ASICs) and digital signal processing (DSP) systems, are typically provided with a large number of sequential elements that perform various logic functions, such as mathematic operations. A clock signal, known as a “global” clock signal, may be used as a timing reference to synchronize data or logic operations performed by these elements positioned at different locations (points), or destinations, on the chip.
A major challenge in such circuit designs is to distribute a “global” clock signal to the elements through different interconnect segments across the chip with minimal clock inaccuracy, particularly when the operating frequency of the chip and the frequency of the “global” clock signal are high. Clock inaccuracy often results in one clock edge not arriving at a sampling point on the chip at its nominal time, measured relative to another clock edge. One type of clock inaccuracy is commonly referred to as clock “skew”. Clock “skew” within a chip is the difference in time that the “global” clock signal reaches different locations (points) on the chip. There are a number of factors for causing clock “skew”, including, for example, electromagnetic propagation delays, buffer delays in the distribution network, resistive-capacitive (RC) delays associated with various distribution lines in the distribution network, and variations in the manufacturing process, temperature gradients, power supply and load capacitance. Another type of clock inaccuracy is referred to as clock “jitter”. Clock “jitter” is the distortion in clock cycle and phase difference accumulated over time (distance), and can be exacerbated by variations caused by noise.
Conventional clock distribution networks typically employ tree-based topology networks, grid-based topology networks, or specific combinations of trees and grids for clock distribution. Many conventional clock distribution networks are designed and implemented specifically for either centralized or distributed skew compensation, while a few active clock distribution networks are currently proposed by academic researchers using multiple oscillators for either centralized or distributed jitter filtering operation.
Clock distribution networks with centralized skew compensation strategies usually rely on a centralized controller (skew compensator) to ensure that clock pulses sent to every clock region on the chip arrive at the expected time. However, distortion can occur, given the wire lengths or relatively long distances between the skew compensator and different clock regions on the chip. A more practical alternative to clock distribution networks with centralized skew compensation is distributed skew compensation in which clock “skew” is compensated at each clock region on the chip.
Similarly, clock distribution networks with centralized jitter filtering strategies rely on a single centralized attenuation filter to filter the jitter accumulation from multiple individual oscillators. The phase signals generated by the individual oscillators are averaged to produce the clock delivered to the sequential elements on the chip. However, noise can propagate, given the wire lengths or relatively long distances between the attenuation filter and different oscillators at different clock regions on the chip. An alternative to centralized jitter filtering is the use of multiple filters distributed at different clock regions for jitter attenuation.
Both types of clock distribution networks rely on analog feedback mechanisms for either centralized or distributed jitter filtering. As a result, clock distribution networks for either centralized or distributed jitter filtering suffer from a large number of significant practical shortcomings. For example, the clock distribution networks are very complex and difficult to implement in practice, sensitive to noise and distortion caused by the transmission of feedback signals over relatively long distances to synchronize the oscillators, susceptible to mode-locking (i.e., an undesirable stable equilibrium in which not all the oscillators have the same phase), and are incompatible with established design-for-testability (DFT) and design-for-debugability (DFD) techniques.
A recent clock distribution network design that incorporates both the clock skew compensation and jitter filtering strategies is disclosed by V. Gutnik, and A. P. Chandrakasan, “Active GHz Clock Network Using Distributed PLLs”, IEEE Journal of Solid-State Circuits, November 2000, pp. 1553-1560. According to Gutnik, a multi-PLL distribution network is provided with an array of synchronized phase-locked loops (PLLs) at multiple locations (points) across the chip. Each PLL feeds a local clock region, and phase detectors (PDs) are inserted between adjacent clock regions for analog feedback and clock alignment. However, the multi-PLL distribution network as described by Gutnick does not distribute individual clock pulses and is not compatible with established design-for-testability (DFT) and design-for-debugability (DFD) techniques.
Therefore, a need exists for a new clock distribution network for clock distribution in an IC chip implemented for both skew compensation and jitter filtering that are compatible with established design-for-testability (DFT) and design-for-debugability (DFD) techniques.